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rf & protection devices data sheet revision 3.1, 2014-03-25 BGT24MR2 silicon germanium 24 ghz twin iq receiver mmic
edition 2014-03-25 published by infineon technologies ag 81726 munich, germany ? 2014 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
BGT24MR2 silicon germanium 24 ghz twin iq receiver mmic data sheet 3 revision 3.1, 2014-03-25 trademarks of infineon technologies ag aurix?, bluemoon?, c166?, ca npak?, cipos?, cipurse?, comn eon?, econopack?, coolmos?, coolset?, corecontrol?, crossave?, dave?, easypim?, econobri dge?, econodual?, econopim?, eicedriver?, eupec?, fcos?, hitfe t?, hybridpack?, i2rf?, isoface?, isopack?, mipaq?, modstack?, my-d?, novalithic?, omnitune?, optimos?, origa?, primarion?, primepack?, primestack?, pr o-sil?, profet?, rasic?, re versave?, satric?, sieget?, sindrion?, sipmos?, smarti?, smartlew is?, solid flash?, tempfet?, thinq!?, trenchstop?, tricore?, x-go ld?, x-pmu?, xmm?, xposys?. other trademarks advance design system? (ads) of agilent te chnologies, amba?, arm?, multi-ice?, keil?, primecell?, realview?, thumb?, vision? of arm limited, uk. autosar? is licensed by autosar development partnership. bluetooth? of bluetooth sig inc. cat-iq? of dect forum. colossus?, firstgps? of trimble navigation ltd. emv? of emvc o, llc (visa holdings in c.). epcos? of epcos ag. flexgo? of microsoft corp oration. flexray? is licensed by flexray consortium. hyperterminal? of hilgraeve incorporated. iec? of commission electrot echnique internationale. irda? of infrared data association corporation. iso? of international organization for standardization. matlab? of mathworks, inc. maxim? of maxim integrated products, inc. microtec?, nucleus? of mentor graphics corporation. mifare? of nx p. mipi? of mipi alliance, inc. mips? of mips technologies, inc., usa. murata? of murata manufacturing co., microwave offi ce? (mwo) of applied wave research inc., omnivision? of omnivision technologies, inc. open wave? openwave systems inc. red hat? red hat, inc. rfmd? rf micro devices, inc. sirius? of sirius sate llite radio inc. solaris? of sun microsystems, inc. spansion? of spansion llc ltd. symbian? of sy mbian software limited. taiyo yuden? of taiyo yuden co. teaklite? of ceva, inc. t ektronix? of tektroni x inc. toko? of toko kabushiki kaisha ta. unix? of x/open company limited. verilog?, palladium? of cadence design systems, inc. vlynq? of texas instruments inco rporated. vxworks?, wind river? of wind river systems, inc. zetex? of diodes zetex limited. last trademarks update 2010-10-26 BGT24MR2 silicon germanium 24 ghz twin iq receiver mmic revision history: 2014-03-25, revision 3.1 previous revision: 2013-07-08, revision 3.1 page subjects (major cha nges since last revision) 7 update feature list
BGT24MR2 silicon germanium 24 ghz twin iq receiver mmic table of contents data sheet 4 revision 3.1, 2014-03-25 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 esd integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 measured rf characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4.1 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4.2 rx section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.5 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 application circuit and block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 application circuit schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4 application board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.5 equivalent circuit diagram of mmic interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4 physical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1 package footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2 reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.3 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table of contents
BGT24MR2 silicon germanium 24 ghz twin iq receiver mmic list of figures data sheet 5 revision 3.1, 2014-03-25 figure 1 BGT24MR2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2 application circuit with chip outlin e (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 3 timing diagram of the spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 4 cross-section view of application board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 5 detail of compensation structure (valid for a ppl. board mat. ro4350b, 0.254mm acc. to fig. 4) . 18 figure 6 application board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 7 equivalent circuit diagram of mmic interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 8 recommended footprint and stenc il layout for the vqfn32-9 package . . . . . . . . . . . . . . . . . . . 21 figure 9 reflow profile for BGT24MR2 (vqfn32- 9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 10 package outline (top, side and bott om view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 11 marking layout vqfn32-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 12 tape of vqfn32-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 list of figures
BGT24MR2 silicon germanium 24 ghz twin iq receiver mmic list of tables data sheet 6 revision 3.1, 2014-03-25 table 1 absolute maximum ra tings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3 esd integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4 typical characteristics t a = -40 .. 105 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 5 typical characteristics t a = -40 .. 105 c, f = 24.0 .. 24.25 ghz . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 6 typical characteristics temperature sensor t a = -40 .. 105 c . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 7 bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 8 pin definition and function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 9 spi data bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 10 spi timing and logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 list of tables
product name package chip marking BGT24MR2 vqfn32-9 t1525 BGT24MR2 silicon germanium 24 ghz twin iq receiver mmic BGT24MR2 data sheet 7 revision 3.1, 2014-03-25 1 features ? gilbert based dual homodyne quadrature receiver ? single ended rf terminals ? low noise figure: nf ssb : 12 db ? high conversion gain: 26 db ? high 1 db input compression point: -12 dbm ? low lo input power ? single supply voltage of 3.3 v ? integrated temperature sensor for monitoring purposes ? power consumption 300 mw in continuous operating mode ? 200 ghz bipolar sige:c technology b7hf200 ? fully esd protected device ? vqfn-32-9 leadless plastic package incl. lti-feature ? pb-free (rohs compliant) package description the BGT24MR2 is a silicon germanium mmic (dual c hannel receiver) accommod ating two se parate homodyne quadrature downconversion chains, operating from 24.0 to 24.25 ghz. it comple ments infineons transceiver mmics bgt24mtr11 and bgt24mtr12. lo buffer amplifie rs are included to relax lo drive requirements and individual lnas provide low noise figures. rc polyphase filters (ppf ) are used for lo quadrature phase generation. the circuit is manufactured in a 0.18m sige :c technology offering a cutoff frequency of 200 ghz. the mmic is packaged in a 32 pin leadless rohs compliant vqfn package.
BGT24MR2 silicon germanium 24 ghz twin iq receiver mmic features data sheet 8 revision 3.1, 2014-03-25 figure 1 BGT24MR2 block diagram BGT24MR2_chip_bid.vsd si cs clk ppf * lna 90 0 lo buffer ppf * lna ifix 2 ifq x 2 90 0 rfin2 lo buffer power s p litte r loin ifq 2 ifi 2 ifix 1 ifq x 1 ifq1 ifi 1 rfin 1 te mp sensor te mp spi 3 * poly phase filter
BGT24MR2 silicon germanium 24 ghz twin iq receiver mmic electrical characteristics data sheet 9 revision 3.1, 2014-03-25 2 electrical characteristics 2.1 absolute maximum ratings t a = -40 c to 105 c; all voltages with respect to grou nd, positive current flowing into pin (unless otherwise specified) 1) attention: stresses exceeding the max. values listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. 1) not subject to production test, specified by design table 1 absolute maximum ratings parameter symbol values unit note / test condition min. typ. max. supply voltage v cc -0.3 ? 3.6 v ? dc voltage at pins rfin1, rfin2, loin vdc rf 0 ? 0 v mmic provides short circuit to gnd for all rf pins dc voltage at pins ifi1/2, ifix1/2, ifq1/2, ifqx1/2 vdc if 0?vccv? dc current into pins ifi1/2, ifix1/2, ifq1/2, ifqx1/2 i if -8.5 ? 3.5 ma max. values indicate current due to short circuit to gnd and vcc respectively dc voltage at pin temp vdc temp -0.3 ? 3.6 v ? dc current into pin temp i temp -1 ? 1.5 ma max. values indicate current due to short circuit to gnd and vcc respectively dc voltage at spi input pins si, clk, cs vdc spiin -0.3 ? 3.6 v ? dc current into spi input pins si, clk, cs i spiin ??3ma? rf input power into pins rfin1, rfin2 p rf ??0dbm? lo input power into pin loin p lo ? ? 10 dbm ? total power dissipation p diss ? ? 500 mw with bist deactivated junction temperature t j -40 ? 150 c ? ambient temperature range t a -40 ? 105 c t a = package soldering point storage temperature range t stg -40 ? 150 c ?
BGT24MR2 silicon germanium 24 ghz twin iq receiver mmic electrical characteristics data sheet 10 revision 3.1, 2014-03-25 2.2 thermal resistance 2.3 esd integrity table 2 thermal resistance parameter symbol values unit note / test condition min. typ. max. junction - soldering point 1) 1) for calculation of r thja please refer to application note thermal resistance r thjs ??40k/w? table 3 esd integrity parameter symbol values unit note / test condition min. typ. max. esd robustness, hbm 1) 1) according to ansi/esda/jedec js-001 (r = 1.5k , c = 100pf) for electrostatic discharge sensitivity testing, human body model (hbm)-component level v esd-hbm -1 ? 1 kv all pins esd robustness, cdm 2) 2) according to jedec jesd22-c101 field-induced charged device model (cdm), test method for electrostatic-discharge- withstand thresholds of microelectronic components v esd-cdm -500 ? 500 v all pins
BGT24MR2 silicon germanium 24 ghz twin iq receiver mmic electrical characteristics data sheet 11 revision 3.1, 2014-03-25 2.4 measured rf characteristics 2.4.1 power supply 2.4.2 rx section table 4 typical characteristics t a = -40 .. 105 c parameter symbol values unit note / test condition min. typ. max. supply voltage v cc 3.135 3.3 3.465 v ? supply current i cc 70 90 120 ma ? table 5 typical characteristics t a = -40 .. 105 c, f = 24.0 .. 24.25 ghz 1) parameter symbol values unit note / test condition min. typ. max. rfin and loin frequency range f rfin, f loin 24.0 ? 24.25 ghz ? rfin and loin port impedance 2) z rfin1 z rfin2 z loin ? 14.0-j4.8 14.9-j6.3 27.3+j9.9 ? typical value at 24.125ghz and vswr 2:1 rfin and loin vswr vswr rfin , vswr loin ? ? 2:1 ? at source port of off chip compensation network as pro- posed if frequeny range f if 0?10mhz? if 1/f corner frequency f c ?1020khz? if port impedance z if 850 1000 1150 ? leakage loin to rfin l loin-rfin ? ? -30 dbm parameter based on ifx eval board design isolation rfin1 to rfin2 i rfin1-rfin2 30 ? ? db parameter based on ifx eval board design loin input power p loin -7 ? 3 dbm ? voltage conversion gain 3) g c 19 26 31 db r load,if > 10k lna gain reduction g clg 358db ? ssb noise figure nf ssb ? 12 20 db single sideband at 100khz 1db input compression ip -1db -17 -12 ? dbm ? 3?rd order input intercept point iip3 -8 -4 ? dbm ?
BGT24MR2 silicon germanium 24 ghz twin iq receiver mmic electrical characteristics data sheet 12 revision 3.1, 2014-03-25 2.5 temperature sensor monitoring of the chip temperature is provided by t he on-chip temperature sensor which delivers temperature- proportional voltage to the temp output. quadrature phase imbalance p -10 ? 10 deg ? quadrat. amplitude imbalance a -1 ? 1 db ? 1) performance based on application circuit figure 2 on pa ge 13, cross section of app lication board, compensation structures and application board layout figur e 4 on page 18ff and footprint figure 8 on page 21 2) guaranteed by device design 3) lowest gain at high temperatur e, highest gain at low temperature table 6 typical characteristics temperature sensor t a = -40 .. 105 c 1) 1) all voltages with respect to ground, positive curr ent flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition min. typ. max. temperature range t tsens -40 ? 105 c ? output temperature voltage v out,temp ? 1.50 ? v @ 25c sensitivity s tsens ?4.5?mv/k? overall accuracy error e rr tsens ?? 15 k ? table 5 typical characteristics t a = -40 .. 105 c, f = 24.0 .. 24.25 ghz 1) (cont?d) parameter symbol values unit note / test condition min. typ. max.
BGT24MR2 silicon germanium 24 ghz twin iq receiver mmic application circuit and block diagram data sheet 13 revision 3.1, 2014-03-25 3 application circuit and block diagram 3.1 application ci rcuit schematic figure 2 application circuit with chip outline (top view) BGT24MR2_appl_bid.vsd n.c. 5) test pin 1) test pin 1) vee loin vee temp ifix1 ifi1 ifq1 ifqx1 vee n.c. 4) vee rfin1 vee rfin2 vee n.c. 4) vcc 2) ifix2 ifi2 ifq2 ifqx2 vee 12 34 5 6 10 89 7 15 12 13 14 17 18 16 11 19 20 29 26 28 27 25 24 23 22 21 30 31 32 c1 1f c2 3) 470f n.c. 5) vee vcc 2) c3 1f 1) connect test pin 24 and 25 2) galvanic connection of vcc pins on silicon (pin 5, 6 and 17) 3) optional value: according to quality of supply voltage (c2) 4) recommendation: connect pin 1 and 10 to vee for better rf performance 5) floating pin 16 and 26 - do not connect with any other pin si clk cs
BGT24MR2 silicon germanium 24 ghz twin iq receiver mmic application circuit and block diagram data sheet 14 revision 3.1, 2014-03-25 table 7 bill of materials part number part type manufacturer size comment c1 ... c3 chip capacitor various various ?
BGT24MR2 silicon germanium 24 ghz twin iq receiver mmic application circuit and block diagram data sheet 15 revision 3.1, 2014-03-25 3.2 pin description table 8 pin definition and function pin no. name function 1 n.c. not connected 2 vee ground 3 rfin1 rf input downconverter 1 4 vee ground 5 vcc supply voltage 6 vcc supply voltage 7 vee ground 8 rfin2 rf input downconverter 2 9 vee ground 10 n.c. not connected 11 vee ground 12 ifqx2 complementary quadrature phase if output downconverter 2 13 ifq2 quadrature phase if output downconverter 2 14 ifi2 in phase if output downconverter 2 15 ifix2 complementary in phase if output downconverter 2 16 n.c. do not connect; dc coupled pin 17 vcc supply voltage 18 cs chip select inpu t spi (inverted) 19 clk clock input spi 20 si data input spi 21 vee ground 22 loin lo input 23 vee ground 24 test pin test pin; dc coupled pin 25 test pin test pin; dc coupled pin 26 n.c. do not connect; dc coupled pin 27 temp temperature sensor output 28 ifix1 complementary in phase if output downconverter 1 29 ifi1 in phase if output downconverter 1 30 ifq1 quadrature phase if output downconverter 1 31 ifqx1 complementary quadratrue phase if output downconverter 1 32 vee ground
BGT24MR2 silicon germanium 24 ghz twin iq receiver mmic application circuit and block diagram data sheet 16 revision 3.1, 2014-03-25 3.3 spi 1.) three signals control the serial peripheral interface of the BGT24MR2: si (data); clk (clock); cs (chip select) 2.) the data bits si (msb first) are read in the shift register with falling edge of the clk signal. please make sure, that the data is present at least 10 ns before and at least 10 ns after the falling edge of the clock signal. 3.) the clk and cs signals are combined internally. at least 20 ns before first rising edge of the first clk signal cs needs to be in "low" state. while the data is read, cs has to remain in "low" state. 4.) when data read in is fi nished, the shift register content will be written in the latch at the ri sing edge of the cs signal. the time between the last falling edge of the clk signal and t he rising edge of the cs must be at least 20 ns. table 9 spi data bit description data bit name description (logic high) power on state 15 (msb) gs lna gain reduction low 14 ? not used low 13 test bit test bit, must be low otherwise malfunction low 12 test bit test bit, must be low otherwise malfunction low 11 test bit test bit, must be low otherwise malfunction low 10 test bit test bit, must be high otherwise malfunction high 9 test bit test bit, must be high otherwise malfunction high 8 test bit test bit, must be high otherwise malfunction high 7 test bit test bit, must be low otherwise malfunction low 6 test bit test bit, must be low otherwise malfunction low 5 test bit test bit, must be low otherwise malfunction low 4 test bit test bit, must be high otherwise malfunction high 3 test bit test bit, must be low otherwise malfunction low 2 test bit test bit, must be high otherwise malfunction high
BGT24MR2 silicon germanium 24 ghz twin iq receiver mmic application circuit and block diagram data sheet 17 revision 3.1, 2014-03-25 figure 3 timing diagram of the spi 1 test bit test bit, must be low otherwise malfunction low 0 test bit test bit, must be low otherwise malfunction low table 10 spi timing and logic levels parameter symbol values unit min. typ. max. serial clock frequency f sclk 0?50mhz serial clock high time f sclk(h) 10 ? ? ns serial clock low time t sclk(l) 10 ? ? ns chip select lead time t cs(lead) 20 ? ? ns chip select lag time t cs(lag) 20 ? ? ns data setup time t si(su) 10 ? ? ns data hold time t si(h) 10 ? ? ns low level (si, clk, cs ) v in(l) 0?0.8v high level (si, clk, cs ) v in(h) 2.0 ? v cc v input capacitance (si, clk, cs ) c in ??2pf input current (si, clk, cs ) i in -150 ? 150 a table 9 spi data bit description (cont?d) data bit name description (logic high) power on state BGT24MR2_spi.vsd
BGT24MR2 silicon germanium 24 ghz twin iq receiver mmic application circuit and block diagram data sheet 18 revision 3.1, 2014-03-25 3.4 application board figure 4 cross-section view of application board figure 5 detail of compensation structure (valid for appl. board mat. ro4350b, 0.254mm acc. to fig. 4) copper 35um blind-vias vias ro4350b, 0.254mm fr4, 0.5mm BGT24MR2_cross_section_view.vsd fr4, 0.25mm BGT24MR2_vqfn32-9-cs.vsd 0.30 0.35 single-ended rfin single-ended loin 0.30 1.85 0.65 1.60 1.00 0.50 0.50 0.30 all specified values in [mm]
BGT24MR2 silicon germanium 24 ghz twin iq receiver mmic application circuit and block diagram data sheet 19 revision 3.1, 2014-03-25 figure 6 application board layout note: in order to achieve the same performance as give n in this datasheet please follow the suggested pcb- layout. the compensation structure is critical for rf performance. via holes as recommended on one of next pages (not shown above). top layer (top view) BGT24MR2_app_board_layout.vsd mid1 and bottom layer (top view) mid2 layer (top view)
BGT24MR2 silicon germanium 24 ghz twin iq receiver mmic application circuit and block diagram data sheet 20 revision 3.1, 2014-03-25 3.5 equivalent circuit diag ram of mmic interfaces figure 7 equivalent circuit diagram of mmic interfaces BGT24MR2_esb.vsd rfin1, rfin2, loin vee pin 3 , 8 , 22 ifx vee vcc pin 12 , 13 , 14 , 15 , 28 , 29 , 30 , 31 400 temp vee vcc pin 27 1500 40 cs, clk, si vee vcc pin 18 , 19 , 20 54k tolerance of all resistors +/- 20%
BGT24MR2 silicon germanium 24 ghz twin iq receiver mmic physical characteristics data sheet 21 revision 3.1, 2014-03-25 4 physical characteristics 4.1 package footprint figure 8 recommended footprint and stencil layout for the vqfn32-9 package BGT24MR2_vqfn32-9-fp.vsd 0.5 0.3 0.85 0.3 2.9 3.3 3.9 4.3 1.0 2.2 3.2 0.1 0.2 copper solder mask vias pastefree area 0.7 0.1 pin 1 all specified values in [mm]
BGT24MR2 silicon germanium 24 ghz twin iq receiver mmic physical characteristics data sheet 22 revision 3.1, 2014-03-25 4.2 reflow profile soldering process qualified during qualification with ?pre conditioning msl-3: 30c. 60%r.h., 192h, according to jedec jstd20?. figure 9 reflow profile for BGT24MR2 (vqfn32-9) BGT24MR2_reflow_profile.vsd reflow profile recommended by infineon technologies ag (based on ipc/jedec j-std-020c)
BGT24MR2 silicon germanium 24 ghz twin iq receiver mmic physical characteristics data sheet 23 revision 3.1, 2014-03-25 4.3 package dimensions figure 10 package outline (top, side and bottom view) figure 11 marking layout vqfn32-9 BGT24MR2_vqfn32-9-po.vsd all specified values in [mm] BGT24MR2_vqfn32-9_ml.vsd
BGT24MR2 silicon germanium 24 ghz twin iq receiver mmic physical characteristics data sheet 24 revision 3.1, 2014-03-25 figure 12 tape of vqfn32-9 BGT24MR2_vqfn32-9_ct.vsd all specified values in [mm]
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